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Preliminary 0
Typical Applications * 3V Quad-Band GSM Handsets * Commercial and Consumer Systems * Portable Battery-Powered Equipment Product Description
The RF3146 is a high-power, high-efficiency power amplifier module with integrated power control. The device is a self-contained 7mmx7mmx0.9mm lead frame module (LFM) with 50 input and output terminals. The power control function is also incorporated, eliminating the need for directional couplers, detector diodes, power control ASICs and other power control circuitry; this allows the module to be driven directly from the DAC output. The device is designed for use as the final RF amplifier in GSM850, EGSM900, DCS and PCS handheld digital cellular equipment and other applications in the 824MHz to 849MHz, 880MHz to 915MHz, 1710MHz to 1785MHz and 1850MHz to 1910MHz bands. On-board power control provides over 50dB of control range with an analog voltage input; and, power down with a logic "low" for standby operation. Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS
RF3146
QUAD-BAND GSM850/GSM900/DCS/PCS POWER AMP MODULE
* GSM850/EGSM900/DCS/PCS Products * GPRS Class 12 Compatible * Power StarTM Module
-A-
7.00 TYP 6.75 TYP
0.10 C A 2 PLCS
0.08 C
0.70 0.65
0.10 C B 2 PLCS
0.90 0.85 0.05 0.00
2 PLCS 0.10 C B -B2 PLCS 0.10 C A
3.37 TYP 3.50 TYP
Dimensions in mm.
-C-
SEATING PLANE
0.10M C A B
0.60 TYP 0.24 0.60 TYP 0.24
Shaded lead is pin 1.
0.30 0.18
0.50
2.20 1.90
0.30 0.50 TYP 0.30
5.25 4.95
Package Style: LFM, 48-Pin, 7mm x7mmx0.9mm
Features * Integrated VREG * Complete Power Control Solution * +35dBm GSM Output Power at 3.5V
DCS/PCS IN 37 BAND SELECT 40 TX ENABLE 41 VBATT 42 VBATT 43 VRAMP 45 GSM IN 48 Fully Integrated Power Control Circuit
31 DCS/PCS OUT
* +33dBm DCS/PCS Output Power at 3.5V * 60% GSM and 55% DCS/PCS EFF * 7mmx7mmx0.9mm Package Size
Ordering Information
RF3146
6 GSM OUT
RF3146 SB RF3146 PCBA
Quad-Band GSM850/GSM900/DCS/PCS Power Amp Module Power Amp Module 5-Piece Sample Pack Fully Assembled Evaluation Board Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Rev A7 040812 W3
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RF3146
Absolute Maximum Ratings Parameter
Supply Voltage Power Control Voltage (VRAMP) Input RF Power Max Duty Cycle Output Load VSWR Operating Case Temperature Storage Temperature
Preliminary
Rating
-0.3 to +6.0 -0.3 to +1.8 +10 50 10:1 -20 to +85 -55 to +150
Unit
VDC V dBm % C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall Power Control VRAMP
Power Control "ON" Power Control "OFF" VRAMP Input Capacitance VRAMP Input Current Turn On/Off Time TX Enable "ON" TX Enable "OFF" GSM Band Enable DCS/PCS Band Enable
Specification Min. Typ. Max.
Unit
Condition
0.2 15
1.5 0.25 20 10 2 0.5 0.5
1.9
1.9 3.5 1
V V pF A s V V V V V V A mA
Max. POUT, Voltage supplied to the input Min. POUT, Voltage supplied to the input DC to 2MHz VRAMP =VRAMP MAX VRAMP =0.2V to VRAMP MAX
Overall Power Supply
Power Supply Voltage Power Supply Current Specifications Nominal operating limits PIN <-30dBm, TX Enable=Low, Temp=-20C to +85C VRAMP =0.2V, TX Enable=High
Overall Control Signals
Band Select "Low" Band Select "High" Band Select "High" Current TX Enable "Low" TX Enable "High" TX Enable "High" Current 0 1.9 0 1.9 0 2.0 20 0 2.0 1 0.5 3.0 50 0.5 3.0 2 V V A V V A
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Preliminary
Parameter Specification Min. Typ. Max. Unit
RF3146
Condition
Temp=+25 C, VBATT =3.5V, VRAMP =VRAMP MAX, PIN =3dBm, Freq=824MHz to 849MHz, 25% Duty Cycle, Pulse Width=1154s 824 to 849 +34.2 +32.0 MHz dBm dBm 55 +3 -88 -50 -35 -15 -25 % dBm dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 VRAMP =0.2V to VRAMP MAX Spurious<-36dBm, RBW=3MHz Set VRAMP where POUT <34.2dBm into 50 load Set VRAMP where POUT <34.2dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pad VRAMP =0.2V to VRAMP MAX Temp = 25C, VBATT =3.5V, VRAMP =VRAMP MAX Temp=+85 C, VBATT =3.0V, VRAMP =VRAMP MAX At POUT MAX, VBATT =3.5V Maximum output power guaranteed at minimum drive level RBW=100kHz, 869MHz to 894MHz, POUT > +5dBm TXEnable=Low, PIN =+5dBm TXEnable=High, PIN =+5dBm, VRAMP =0.2V VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP MAX
Overall (GSM850 Mode)
Operating Frequency Range Maximum Output Power
Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Cross Band Isolation at 2f0 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability
47 0
+5 -81 -35 -15 -18 -7 -15 -36
50
Output Load VSWR Ruggedness
10:1
Output Load Impedance
50
dB
Power Control VRAMP
Power Control Range 55 Notes: VRAMP MAX =0.4*VBATT +0.06<1.5V VRAMP_RP =VRAMP set for 34.2dBm at nominal conditions.
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RF3146
Parameter Specification Min. Typ. Max. Unit
Preliminary
Condition
Temp=+25 C, VBATT =3.5V, VRAMP =VRAMP MAX, PIN =3dBm, Freq=880MHz to 915MHz, 25% Duty Cycle, Pulse Width=1154s 880 to 915 +34.2 +32.0 MHz dBm dBm 58 +3 -86 -88 % dBm dBm dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 VRAMP =0.2V to VRAMP MAX Spurious<-36dBm, RBW=3MHz Set VRAMP where POUT <34.2dBm into 50 load Set VRAMP where POUT <34.2dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pad VRAMP =0.2V to VRAMP MAX Temp = 25C, VBATT =3.5V, VRAMP =VRAMP MAX Temp=+85 C, VBATT =3.0V, VRAMP =VRAMP MAX At POUT MAX, VBATT =3.5V Maximum output power guaranteed at minimum drive level RBW=100kHz, 925MHz to 935MHz, POUT > +5dBm RBW=100kHz, 935MHz to 960MHz, POUT > +5dBm TXEnable=Low, PIN =+5dBm TXEnable=High, VRAMP =0.2V, PIN =+5dBm VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP MAX
Overall (GSM900 Mode)
Operating Frequency Range Maximum Output Power
Total Efficiency Input Power Range Output Noise Power
54 0
+5 -80 -84 -35 -15 -17 -10 -15 -36
Forward Isolation 1 Forward Isolation 2 Cross Band Isolation 2f0 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability
-45 -30 -15 -25
50
Output Load VSWR Ruggedness
10:1
Output Load Impedance
50
dB
Power Control VRAMP
Power Control Range 50 Notes: VRAMP MAX =0.4*VBATT +0.06<1.5V VRAMP_RP =VRAMP set for 34.2dBm at nominal conditions.
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Preliminary
Parameter Specification Min. Typ. Max. Unit
RF3146
Condition
Temp=25C, VBATT =3.5V, VRAMP =VRAMP MAX, PIN =3dBm, Freq=1710MHz to 1785MHz, 25% Duty Cycle, pulse width=1154s 1710 to 1785 +32.0 30 MHz dBm dBm 52 +3 -85 -50 -25 -15 -20 % dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 VRAMP =0.2V to VRAMP MAX Spurious<-36dBm, RBW=3MHz Set VRAMP where POUT <32.0dBm into 50 load Set VRAMP where POUT <32.0dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pin VRAMP =0.2V to VRAMP MAX, PIN =+5dBm Temp=25C, VBATT =3.5V, VRAMP =VRAMP MAX Temp=+85C, VBATT =3.0V, VRAMP =VRAMP MAX At POUT MAX, VBATT =3.5V Maximum output power guaranteed at minimum drive level RBW=100kHz, 1805MHz to 1880MHz, POUT > 0dBm, VBATT =3.5V TXEnable=Low, PIN =+5dBm TXEnable=High, VRAMP =0.2V, PIN =+5dBm VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP MAX
Overall (DCS Mode)
Operating Frequency Range Maximum Output Power
Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability
45 0
+5 -80 -35 -15 -7 -15 -36
50
Output Load VSWR Ruggedness
10:1
Output Load Impedance
50
dB
Power Control VRAMP
Power Control Range 50 Notes: VRAMP MAX =0.4*VBATT +0.06<1.5V VRAMP_RP =VRAMP set for 32.0dBm at nominal conditions.
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RF3146
Parameter Specification Min. Typ. Max. Unit
Preliminary
Condition
Temp=25C, VBATT =3.5V, VRAMP =VRAMP MAX, PIN =3dBm, Freq=1850MHz to 1910MHz, 25% Duty Cycle, pulse width=1154s 1850 to 1910 +32.0 30 MHz dBm dBm 55 +3 -85 -40 -20 -15 -20 % dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 VRAMP =0.2V to VRAMP MAX Spurious<-36dBm, RBW=3MHz Set VRAMP where POUT <32.0dBm into 50 load Set VRAMP where POUT <32.0dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pin VRAMP =0.2V to VRAMP MAX, PIN =+5dBm Temp=25C, VBATT =3.5V, VRAMP =VRAMP MAX, 1850MHz to 1910MHz Temp=+85C, VBATT =3.0V, VRAMP =VRAMP MAX At POUT MAX, VBATT =3.5V Full output power guaranteed at minimum drive level RBW=100kHz, 1930MHz to 1990MHz, POUT > 0dBm, VBATT =3.5V TX_ENABLE=Low, PIN =+5dBm TXEnable=High, VRAMP =0.2V, PIN =+5dBm VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP_RP VRAMP =0.2V to VRAMP MAX
Overall (PCS Mode)
Operating Frequency Range Maximum Output Power
Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability
48 0
+5 -80 -33 -15 -7 -15 -36
50
Output Load VSWR Ruggedness
10:1
Output Load Impedance
50
dB
Power Control VRAMP
Power Control Range 50 Notes: VRAMP MAX =0.4*VBATT +0.06<1.5V VRAMP_RP =VRAMP set for 32.0dBm at nominal conditions.
2-496
Rev A7 040812 W3
Preliminary
Pin 1 2
RF3146
Function Description Interface Schematic Internal circuit node. Do not externally connect. NC VCC2 GSM Controlled voltage input to the GSM driver stage. This voltage is part of VCC2
the power control function for the module. This node must be connected to VCC OUT. This pin should be externally decoupled.
3 4 5 6
NC GND GND GSM850/ GSM900 OUT GND NC NC NC NC NC NC NC NC NC NC VCC3 GSM
Internal circuit node. Do not externally connect. Internally connected to the package base. Internally connected to the package base. RF output for the GSM bands. This is a 50 output. The output matching circuit and DC-block are internal to the package.
VCC3
Output Match
RF OUT
7 8 9 10 11 12 13 14 15 16 17 18
Internally connected to the package base. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. No internal or external connection. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Controlled voltage input to the GSM output stage. This voltage is part of the power control function for the module. This node must be connected to VCC OUT. This pin should be externally decoupled.
VCC3
19 20 21 22 23 24 25 26 27 28 29 30
VCC OUT VCC OUT VCC3 DCS/PCS NC NC NC NC NC NC NC NC GND
Controlled voltage output to feed VCC2 and VCC3. This voltage is part of the power control function for the module. It cannot be connected to any pins other than VCC2 and VCC3. Controlled voltage output to feed VCC2 and VCC3. This voltage is part of the power control function for the module. It cannot be connected to any pins other than VCC2 and VCC3. Controlled voltage input to the DCS/PCS output stage. This voltage is part of the power control function for the module. This node must be connected to VCC OUT. This pin should be externally decoupled. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. No internal or external connection. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internal circuit node. Do not externally connect. Internally connected to the package base.
See pin 18.
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RF3146
Pin 31 32 33 34 35 36 37 Function DCS/PCS OUT GND NC GND VCC2 DCS/PCS NC DCS/PCS IN Description
RF output for the DCS/PCS bands. This is a 50 output. The output matching circuit and DC-block are internal to the package. Internally connected to the package base. Internal circuit node. Do not externally connect. Internally connected to the package base. Controlled voltage input to the DCS/PCS driver stage. This voltage is part of the power control function for the module. This node must be connected to VCC OUT. This pin should be externally decoupled. No internal connection. Connect to ground plane close to the package pin. RF input to the DCS/PCS band. This is a 50 output.
Preliminary
Interface Schematic
See pin 6.
See pin 2.
VCC1
RF IN
38 39
NC VCC1 DCS/PCS
No internal connection. Connect to ground plane close to the package pin. Controlled voltage on the GSM and DCS/PCS preamplifier stages. This voltage is applied internal to the package. This pin should be externally decoupled.
VCC1
40
BAND SEL
Allows external control to select the GSM or DCS/PCS bands with a logic high or low. A logic low enables the GSM bands, whereas a logic high enables the DCS/PCS bands.
BAND SEL TX EN
GSM CTRL
DCS CTRL
41
TX ENABLE
This signal enables the PA module for operation with a logic high. Both bands are disabled with a logic low.
TX EN
VBATT
TX ON
42 43 44 45
VBATT VBATT NC VRAMP
Power supply for the module. This pin should be externally decoupled and connected to the battery. Power supply for the module. This pin should be externally decoupled and connected to the battery. Internal circuit node. Do not externally connect. Ramping signal from DAC. A simple RC filter may be required depending on the selected baseband.
VRAMP +
46 47 48 Pkg Base
VCC1 GSM GND1 GSM GSM850/ GSM900 IN GND
Internally connected to VCC1 (pin 39). No external connection required. Ground connection for the GSM preamplifier stage. Connect to ground plane close to the package pin. RF input to the GSM band. This is a 50 input. Connect to ground plane with multiple via holes. See recommended footprint.
See pin 39.
See pin 37.
2-498
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Preliminary
Pin Out
DCS/PCS IN TX ENABLE GND1 GSM GSM850/ GSM900 IN BAND SEL vcc1 GSM VCC1 DCS/PCS
RF3146
VRAMP
VBATT
VBATT
NC
48 NC 1 VCC2 GSM 2 NC 3 GND 4 GND 5 GSM850/ 6 GSM900 OUT GND 7 NC 8 NC 9 NC 10 NC 11 NC 12 13 NC
47
46
45
44
43
42
41
40
39
38
NC
37 36 NC 35 VCC2 DCS/PCS
34 GND 33 NC 32 GND 31 DCS/PCS OUT 30 GND 29 NC 28 NC 27 NC 26 NC 25 NC 14 NC 15 NC 16 NC 17 NC 18 VCC3 GSM 19 VCC OUT 20 VCC OUT 21 VCC3 DCS/PCS 22 NC 23 NC 24 NC
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RF3146
Application Schematic
TX EN VBATT VRAMP 15 k GSM850/ GSM900 IN 48 1 2 1 nF 3 4 5 GSM850/ GSM900 OUT 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Fully Integrated Power Control Circuit
From VCC1
Preliminary
BAND SEL VCC1 1 nF
VCC1: Internally supplied. See Pin Function note.
4.7 F
DCS/PCS IN 47 46 45 44 43 42 41 40 39 38 37 36
VCC
35 34 33 32 31 30 29 28 27 26 25 DCS/PCS OUT 1 nF
10 nF 100 pF
2-500
Rev A7 040812 W3
Preliminary
Evaluation Board Schematic
TX EN R3 100 k VRAMP VBATT VCC1 R2 100 k
RF3146
BAND SEL
GSM850/ GSM900 IN
50 strip 48 1 2 C9 1 nF 3 4 5
From VCC1
R4 100 k
R1 15 k
C2 4.7 F 44 43 42 41 40 39
C6 1 nF 38 37
VCC1: Internally supplied. See Pin Function note.
50 strip DCS/PCS IN
47
46
45
36
VCC
35 34 33 32 50 strip 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 DCS/PCS OUT C4 DNP C8 1 nF
GSM850/ GSM900 OUT
50 strip 6 7 8 9 10 11 12
C13 100 pF
C10 10 nF
Rev A7 040812 W3
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RF3146
Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.032", Board Material FR-4, Multi-Layer
Preliminary
2-502
Rev A7 040812 W3
Preliminary
Theory of Operation
RF3146
Overview The RF3146 is a quad-band GSM850, EGSM900, DCS1800, and PCS1900 power amplifier module that incorporates an indirect closed loop method of power control. This simplifies the phone design by eliminating the need for the complicated control loop design. The indirect closed loop appears as an open loop to the user and can be driven directly from the DAC output in the baseband circuit. Theory of Operation The indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power control systems in GSM sense either forward power or collector/drain current. The RF3146 does not use a power detector. A high-speed control loop is incorporated to regulate the collector voltage of the amplifier while the stage are held at a constant bias. The VRAMP signal is multiplied by a factor of 2.65 and the collector voltage for the second and third stages are regulated to the multiplied VRAMP voltage. The basic circuit is shown in the following diagram.
VBATT TX ENABLE VRAMP
H(s)
RF IN TX ENABLE
RF OUT
By regulating the power, the stages are held in saturation across all power levels. As the required output power is decreased from full power down to 0dBm, the collector voltage is also decreased. This regulation of output power is demonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although load impedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF3146 regulating collector voltage, the dominant mode of power fluctuations is eliminated.
P dBm
( 2 V CC - V SAT ) = 10 log -------------------------------------------3 8 R LOAD 10
2
(Eq. 1)
There are several key factors to consider in the implementation of a transmitter solution for a mobile phone. Some of them are: * * * * * * * * * * Current draw and system efficiency Power variation due to Supply Voltage Power variation due to frequency Power variation due to temperature Input impedance variation Noise power Loop stability Loop bandwidth variations across power levels Burst timing and transient spectrum trade offs Harmonics
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RF3146
Preliminary
Output power does not vary due to supply voltage under normal operating conditions if VRAMP is sufficiently lower than VBATT. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most cases where the PA will be operated. However, as the battery discharges and approaches its lower power range the maximum output power from the PA will also drop slightly. In this case it is important to also decrease VRAMP to prevent the power control from inducing switching transients. These transients occur as a result of the control loop slowing down and not regulating power in accordance with VRAMP. The switching transients due to low battery conditions are regulated by incorporating the following relationship limiting the maximum VRAMP voltage (Equation 2). Although no compensation is required for typical battery conditions, the battery compensation required for extreme conditions is covered by the relationship in Equation 4. This should be added to the terminal software.
V RAMPMAX = 0.4 V BATT + 0.06 1.5V
(Eq. 2)
Due to reactive output matches, there are output power variations across frequency. There are a number of components that can make the effects greater or less. Power variation straight out of the RF3146 is shown in the tables below. The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there is some length of microstrip that follows the power amplifier. There is also a frequency response found in directional couplers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the RF3146 does not use a directional coupler with a diode detector, these variations do not occur. Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where CBE and CCB (CGS and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance variations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCO off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations due to the load variations presented to the VCO. The RF3146 presents a very constant load to the VCO. This is because all stages of the RF3146 are run at constant bias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to the power amplifier. Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 5),
F2 - 1 F3 - 1 F TOT = F1 + --------------- + ------------------G1 G2 G1
(Eq. 3)
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3146 is kept constant the gain in the first stage is always high and the overall noise power is not increased when decreasing output power. Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop involves trade-offs affecting stability, transient spectrum and burst timing. In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidth also varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low slope regions which often causes instability at high slope regions. The RF3146 loop bandwidth is determined by internal bandwidth and the RF output load and does not change with respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage and collector voltage do not vary.
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Preliminary
RF3146
An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the burst timing when, for instance the input power from the VCO decreases (or increases) with respect to temperature or supply voltage. The burst timing then appears to shift to the right especially at low power levels. The RF3146 is insensitive to a change in input power and the burst timing is constant and requires no software compensation. Switching transients occur when the up and down ramp of the burst is not smooth enough or suddenly changes shape. If the control slope of a PA has an inflection point within the output power range or if the slope is simply too steep it is difficult to prevent switching transients. Controlling the output power by changing the collector voltage is as earlier described based on the physical relationship between voltage swing and output power. Furthermore all stages are kept constantly biased so inflection points are nonexistent. Harmonics are natural products of high efficiency power amplifier design. An ideal class "E" saturated power amplifier will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content. Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content as well. With most power control methods a peak power diode detector is used to rectify and sense forward power. Through the rectification process there is additional squaring of the waveform resulting in higher harmonics. The RF3146 address this by eliminating the need for the detector diode. Therefore the harmonics coming out of the PA should represent the maximum power of the harmonics throughout the transmit chain. This is based upon proper harmonic termination of the transmit port. The receive port termination on the T/R switch as well as the harmonic impedance from the switch itself will have an impact on harmonics. Should a problem arise, these terminations should be explored. The RF3146 incorporates many circuits that had previously been required external to the power amplifier. The shaded area of the diagram below illustrates those components and the following table itemizes a comparison between the RF3146 Bill of Materials and a conventional solution.
Component Power Control ASIC Directional Coupler Buffer Attenuator Various Passives Mounting Yield (other than PA) Total Conventional Solution $0.80 $0.20 $0.05 $0.05 $0.05 $0.12 $1.27 RF3146 N/A N/A N/A N/A N/A N/A $0.00
1 2 3 4 5 6 7
14 13 12 11 10 9 8
From DAC
*Shaded area eliminated with Indirect Closed Loop using RF3146
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RF3146
PCB Design Requirements
Preliminary
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.64 x 0.28 (mm) Typ. B = 0.28 x 0.64 (mm) Typ. C = 5.65 (mm) Sq. 5.50 Typ. 0.50 Typ.
Pin 48 Dimensions in mm.
BBBBBBBBBBBB
Pin 1
0.50 Typ.
A A A A A A A A A A A A BBBBBBBBBBBB
A A A A A A A A A A A A
Pin 36
2.75
C
5.50 Typ.
0.55 Typ. 0.55 Typ.
Pin 24
2.75
Figure 1. PCB Metal Land Pattern (Top View)
2-506
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Preliminary
RF3146
PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.74 x 0.38 (mm) Typ. B = 0.38 x 0.74 (mm) Typ. C = 5.25 x 2.20 (mm) 5.50 Typ.
Dimensions in mm.
0.50 Typ.
Pin 48
BBBBBBBBBBBB
Pin 1
Pin 36
0.50 Typ.
0.55 Typ.
A A A A A A A A A A A A
C
A A A A A A A A A A A A
Pin 24
1.95
5.50 Typ.
BBBBBBBBBBBB
0.55 Typ. 2.75
Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
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RF3146
Preliminary
2-508
Rev A7 040812 W3

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Price & Availability of RF3146

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